Sessional 2 | COA | MCA | 24-25

Solutions for Quick Revision

SECTION – A (Very Short Answer Questions — 2 marks each)

Q1. Define Pipelining.
Answer:

• Pipelining is a technique used in CPUs to execute multiple instructions simultaneously.
• The instruction is divided into stages (Fetch, Decode, Execute…), and each stage works in parallel.
• It increases speed and performance of the processor.

Q2. Explain Main Memory.
Answer:

• Main Memory = Primary memory = RAM.
• It stores data and instructions that the CPU is currently using.
• It is volatile, meaning data is lost when power is off.

Q3. Explain Virtual Memory.
Answer:

• Virtual memory is a technique where part of secondary storage (hard disk) works like main memory.
• It allows computers to run bigger programs than RAM capacity.
• Implemented using paging or segmentation.

 SECTION – B (Short Answer Questions — 3 marks each)

Q1. Explain Instruction Cycle with flowchart.
Answer:
An instruction cycle describes how the CPU processes each instruction.

Steps:

1. Fetch: CPU fetches instruction from memory.
2. Decode: CPU interprets instruction and identifies required operation.
3. Execute: CPU performs the operation (arithmetic, memory access, branching etc.).
4. Store Result: Result is stored in register or memory.

Simple Flowchart:
Fetch → Decode → Execute → Store → Next Instruction

Q2. Explain Cache Memory with any one mapping technique.
Answer:
Cache Memory:

• A small, high-speed memory between CPU and main memory.
• Stores frequently used instructions and data.
• Improves CPU speed and reduces access time.

Mapping Technique (example: Direct Mapping):

• Each block of main memory goes to one fixed location in cache.
• Formula: Cache line = (Main memory block number) mod (Number of cache lines).
• Simple and fast, but chances of conflict are high.

Q3. Differentiate RAM & ROM.

SECTION – C (Descriptive — 6 marks each) Do Any One

Q1. Explain Memory Hierarchy and its characteristics.

Memory Hierarchy:
Arrangement of storage devices based on speed, cost, and size.

Levels (Top to Bottom):

1. Registers — Fastest, inside CPU
2. Cache Memory — Very fast, small-sized
3. Main Memory (RAM) — Medium speed, medium size
4. Secondary Memory — Hard disk, SSD, large storage, slower
5. Tertiary Memory — External and backup storage

Characteristics:

• Speed: Highest at top, lowest at bottom
• Cost per bit: Highest at top, lowest at bottom
• Capacity: Low at top, very high at bottom
• Performance: Improves because fast memory is close to CPU

This arrangement gives the best cost–performance balance.

Q2. Explain Booth Multiplication Algorithm in detail.

Booth Algorithm:
Used for multiplication of signed binary numbers.

Main Idea:
It reduces number of addition operations by checking pairs of bits.

Rules:

• If pair = 01 → Add multiplicand
• If pair = 10 → Subtract multiplicand
• If pair = 00 or 11 → No operation
• Then perform Arithmetic Right Shift (ARS)

Steps:

1. Initialize registers (AC, MQ, Q₋₁).
2. Check MQ₀ and Q₋₁ bits.
3. Perform add/subtract based on rules.
4. Right shift.
5. Repeat for number of bits.

Q3. Differentiate Hardwired and Microprogrammed Control Unit.

Hardwired CU:

• Control signals generated using hardware circuits (gates, flip-flops).
• Very fast.
• Difficult to modify.
• Used in RISC processors.

Microprogrammed CU:

• Control signals generated by micro-instructions stored in control memory.
• Slower but flexible.
• Easy to update and modify.
• Used in CISC processors.

 QUIZ (All 6 compulsory — 0.5 mark each)

1. Two phases of executing an instruction:
Ans. (b) Instruction fetch and instruction execution

Q2. Memory used to speed up processing:
Ans. (a) Cache memory

Q3. Subtraction in computer is carried out by:
Ans. (b) 2’s complement

Q4. Temporary storage during working on PC document:
Ans. (c) RAM

Q5. Memory blocks mapped to cache with help of:
Ans. (c) Mapping functions

Q6. If decimal point is placed to right of first digit, number is called:
Ans. (b) Normalized